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ts a7887 page 1 ? 2012 touchstone semiconductor, inc. all rights reserved. features ? alternate s ource for ad7887 ? single - supply operation: + 2.7v to + 5.25v ? inl: 1lsb - TSA7887b 2lsbs - TSA7887a ? one or two single - ended analog inputs ? internal wide - bandwidth track - and - hold ? internal +2.5 - v reference ? flexible power/throughput - rate management 0.85 m a at 125ksps (internal vref on) 0.7ma at 125ksps (internal vref off ) ? shutdown - mode supply current : 1 a ( max ) ? spi?/qspi?/microwire?/dsp - c ompatible serial interface s 1 ? operating temperature range: - 40oc to +125oc ? 8 - pin soic and msop pack aging applications instrumentation and control systems high - speed modems battery - powered systems: personal digital assistants, medical instruments, mobile c ommunications 1 spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corporation description the TSA7887 C a n alternate source for the ad7887 - is a self - contained, 2 - channel, high - speed, micro power, 12 - bit analog - to - digital converter (adc) that operates from a single + 2.7v to + 5.25v power supply. the TSA7887 is capab le of a 125 - k sps throughput rate with an external 2mhz serial clock and draws 0.85ma supply current . the wideband input track - an d - hold acquires signal s in 500 ns and features a single - ended sampling topology . o utput data coding is straight binary and the adc is capable of converting full power signals up to 2.5 mhz. the adc also contains an integrated 2.5v reference or the v ref pin can be over driven by an external reference. the TSA7887s provides one or two analog inputs each with an analog input range f rom 0 to v ref . in two - channel operation, the analog input range is 0v to vdd. efficient circuit design ensures low power consumption of 2 mw (typical) for normal opera tion and 3 w in power - down operation . the TSA7887 is fully specified from - 40 o c to +125 o c and is available in 8 - pin soic and msop packages. a micropower, 2 - channel, 125 - ksps , serial - output 12 - bit sar adc functional block dia gram t he touchstone semicondu c tor logo is a registered trademark of touchstone semiconductor, incorporated.
ts a7887 page 2 TSA7887ds r1p0 rtdfs absolute maximum rat ings v dd to agnd ................................ .............................. ? 0.3 v to + 7 v analog input voltage (ain0, ain1) to agnd .... ? 0.3 v to v dd + 0.3 v digital input voltage to agnd .......................... ? 0.3 v to v dd + 0.3 v digital output voltage to agnd ........................ ? 0.3 v to v dd + 0.3 v refin/refout to agnd ................................ ? 0.3 v to v dd + 0.3 v input current to any pin except supplies 1 ............................ 10 ma operating temperature range a, b versions ................................ .................... ? 40c to +125c storage temperature range ................................ ? 65c to +150c junction temperature ................................ .......................... +150c soic/ msop package power dissipation ............................. 450 mw ja thermal impedance ................................ .... 157c/w (soic) 205.9c/w (msop) jc thermal impedance ................................ ...... 56c/w (soic) 43.74c/w (msop) lead temperature, soldering vapor phase (60 sec) ................................ ....................... 215c infrared (15 sec) ................................ ............................... 220c pb - free temperature, soldering reflow ............................ 260(0)c esd ................................ ................................ ........................... 4 kv electrical and thermal s tresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is not implied. exposure to any absolute maximum rating conditions for extended periods may affect device reliability and lifetime . package/ordering information order number part marking carrier quantity TSA7887arz ts7887a tube 97 TSA7887arz - reel tape & reel 2500 TSA7887brz ts7887b tube 97 TSA7887brz - reel tape & reel 2500 order number part marking carrier quantity TSA7887armz taav tube 50 TSA7887armz - reel tape & reel 2500 lead - free program: touchstone semiconductor su pplies only lead - free packaging. consult touchstone semiconductor for products specified with wider operating temperature ranges.
TSA7887 TSA7887ds r1p0 page 3 rtfds electrical characteristics v dd = + 2.7v to + 5.25v; vref = 2.5v external/internal reference unless otherwise noted; f sclk = 2 mhz; t a = t min to t max , unless otherwise noted. parameter a version 1 b version 1 unit test conditions/comments dynamic performance signal to noise + distortion ratio (snr) 2 71 71 db ( typ) f in = 10 khz sine wave, f sample = 125 ksps total harmonic distortion (thd) ? 80 ? 80 db (typ) f in = 10 khz sine wave, f sample = 125 ksps peak harmonic or spurious noise C 80 ? 80 db (typ) f in = 10 khz sine wave, f sample = 125 ksps intermodulation distortion (imd) second - order terms ? 80 ? 80 db (typ) f1 = 9.983 khz, f2 = 10.05 khz, f sample = 125 ksps third - order terms ? 80 ? 80 db (typ) f1 = 9.983 khz, f2 = 10.05 khz, f sample = 125 ksps channel - to - channel isolation ? 80 ? 80 db (typ) f in = 25 khz full - power bandwidth 2.5 2.5 mhz (typ) measured at 3 db down dc accuracy ( any channel ) resolution 12 12 bits integral nonlinearity 2 1 lsb (max) differential nonlinearity 2 1 lsb (max) guaranteed no missing codes to 11 bits (a grade) offset error 3 3 lsb (max) v dd = 5v, dual - channel mode 4 4 lsb (max) v dd = 3v, dual - channel mode 6 6 lsb (typ) single - channel mode offset error match 0.5 0.5 lsb (max) gain error 2 2 lsb ( typ ) dual - channel mode 1 1 lsb (max) single - channel mode, external reference 6 6 lsb (typ) single - channel mode, internal reference gain error match 2 2 lsb (max) analog input input voltage ranges 0 to v ref 0 to v ref v leakage current 5 5 a (max) input capacitance 1 0 1 0 pf (typ) reference input/output refin input voltage range 2.5/v dd 2.5/v dd v (min/max) functional from 1.2v input impedance 10 10 k (typ) very high impedance if internal reference disabled refout output voltage 2.45/2.55 2.45/2.55 v (min/max) refout temperature coefficient 50 50 ppm/c (typ) logic inputs input high voltage, v inh 2.4 2.4 v (min) v dd = 4.75v to 5.25v 2.1 2.1 v (min) v dd = 2.7v to 3.6v input low voltage, v inl 0.8 0.8 v (max) v dd = 2.7 v to 5.25 v input current, i in 1 1 a (max) typically 10 na, v in = 0 v or v dd input capacitance, c in 3 10 10 pf (max) logic outputs output high voltage, v oh i source = 200 a v dd ? 0.5 v dd ? 0.5 v (min) v dd = 2.7v to 5.25v output low voltage, v ol 0.4 0.4 v (max) i sink = 200 a floating - state leakage current 1 1 a (max) floating - state output capacitance 4 10 10 pf (max) output coding straight (natural) binary conversion rate throughput time 16 16 sclk cycles conversion time plus acquisition time is 125 ksps , with 2 mhz clock track - and - hold acquisition time 1.5 1.5 sclk cycles conversion time 14.5 14.5 sclk cycles 7.25 s (2 mhz clock)
ts a7887 page 4 TSA7887ds r1p0 rtfds electrical specifications (continued) v dd = + 2.7v to + 5.25v; v ref = 2.5v external/internal reference unless otherwise noted; f sclk = 2 mhz; t a = t min to t max , unless otherwise noted. parameter a version 1 b version 1 unit test conditions/comments power requirements v dd +2.7/+5.25 +2.7/+5.25 v (min/max) i dd normal mode 4 ( pm mode 2) static 700 700 a (max) operational (f sample = 125 ksps) 850 850 a (typ) internal reference enabled 700 700 a (typ) internal reference disabled using standby mode ( pm mode 4) 450 450 a (typ) f sample = 50 k sps using shutdown mode ( pm modes 1 and 3) 120 120 a (typ) f sample = 10 k sps 12 12 a (typ) f sample = 1 k sps standby mode 5 210 210 a (max) v dd = 2.7v to 5.25 v shutdown mode 5 1 1 a (max) v dd = 2.7v to 3.6v 2 2 a (max) v dd = 4.75v to 5.25v normal mode power dissipation 3.5 3.5 mw (max) v dd = 5 v 2.1 2.1 mw (max) v dd = 3 v shutdown power dissipation 5 5 w (max) v dd = 5 v 3 3 w (max) v dd = 3 v standby power dissipation 1.05 1.05 mw (max) v dd = 5 v 630 630 w (max) v dd = 3 v note 1: the TSA7887 s temperature range is C 40 c to +1 2 5 c for both a and b ve rsion s. note 2 : snr calculation includes distortion and noise components. note 3 : sample tested at t a = 25 c to ensure compliance. note 4 : all digital inputs at gnd except for cs at v dd . all digital outputs are unloaded. analog inputs are connected to gnd. note 5 : sclk is at gnd when sclk is off. all digital inputs are at gnd except for cs at v dd . all digital outputs are unloaded. analog inputs are connected to gnd.
TSA7887 TSA7887ds r1p0 page 5 rtfds timing specifications 1 parameter limit at t min , t max unit description (a, b versions) 4.75v to 5.25v 2.7v to 3.6v f sclk 2 2 2 mhz (max) t convert 14.5 t sclk 14.5 t sclk t acq 1.5 t sclk 1.5 t sclk throughput time = t convert + t acq = 16 t sclk t 1 10 10 ns (min) cs to sclk setup time t 2 3 30 60 ns (max) delay from cs until dout three - state disabled t 3 3 75 100 ns (max) data access time after sclk falling edge t 4 20 20 ns (min) data setup time prior to sclk rising edge t 5 20 20 ns (min) data valid to sclk hold time t 6 0.4 t sclk 0.4 t sclk ns (min) sclk high pulse width t 7 0.4 t sclk 0.4 t sclk ns (min) sclk low pulse width t 8 4 80 80 ns (max) cs rising edge to dout high - z t 9 5 5 s (typ) power - up time from shutdown note 1: timing specifications are sample tested at 25c to ensure compliance. all input signals are specified with tr = tf = 5 ns (10 % to 90% of v dd ) and timed relative to a voltage level of 1.6v. note 2: the mark/space ratio for the sclk input is 40/60 to 60/40. see serial interface section for additional details. note 3: measured with the load circuit as shown below and defined as the time required for the output to cross 0.8v or 2.0v. note 4: timing specification t 8 is derived from the measured time taken by th e data outputs to change 0.5v when loaded with the circuit shown below . the measured result is then extrapolated back to remove the effects of charging or discharging the 50pf capacitor. this means that the time, t 8 , quoted in the timing characteristics is the true bus relinquish time of the TSA7887 and is independent of bus loading. load circuit used for TSA7887s digital output timing specifications.
ts a7887 page 6 TSA7887ds r1p0 rtfds typical performance characteristics power supply rejection vs frequency power supply rejection - db - 97 - 93 - 89 - 85 - 77 frequency - khz - 81 2.65 23.2 33.7 43.9 12.9 54.4 64.2 vdd = 2.7v/5.5v refin (external) = 2.488v 100mvpp sine wave on vdd vdd = 5v refin (external) = 5v signal - to - noise ratio vs frequency signal - to - noise ratio - db 70 70.5 71 72 71.5 0.7 21.4 31.8 42.1 11 frequency - khz dynamic performance vs frequency fft results - db - 140 - 100 - 80 - 60 - 40 0 frequency - khz - 20 0 20 30 40 10 50 - 120 60 4096 - point fft 125khz sampling rate 10khz fundamental
TSA7887 TSA7887ds r1p0 page 7 rtfds pin functions p in label description 1 cs chip select : a s an active low logic input signal , the cs input provides the dual function of initiating TSA7887 conversions as well as framing the serial data transfer. when the TSA7887 is operate d in mode 1(its default power management mode ) , the cs pin also acts as the shutdown pin in that the TSA7887 is power ed - down w hen the cs pin is logic high . 2 v dd power supply voltage: the TSA7887s v dd range +2.7 v to + 5.25v. in two - channel operation, the vdd pin also serves as the TSA7887s voltage reference source during conversions. for optimal performance, the vdd pin should be bypassed to gnd with a 10 - f tantalum capacitor in parallel with a 0.1f ceramic capacitor. 3 gnd analog ground pin : the gnd pin is the ground reference point for all TSA7887 internal circuitry. in systems with separate agnd and dgnd planes , the TSA7887s gnd pin should be connected to the agnd plane. 4 ain1/v ref analog input channel 1/ external vr ef input : in single - channel mode, the ain1/vref pin is configured as vrefin/out . in this mode , the TSA7887s internal 2.5v reference can be accessed or an external reference can be applied to this pin thereby over riding the internal reference. the reference voltage range for an externally - applied reference is 1.2 v to v dd . in two - channel mode, the ain1/vref pin operates as a second analog input channel, ain1. the input voltage range on ain1 is 0 to v dd . 5 ain0 analog input channel 0 : in single - channel operation , ain0 is the TSA7887s analog input with an input voltage range of 0 v to v ref . in two - channel operation , the ain0 pin exhibits an analog input range of 0 v to v dd . 6 din serial data in put: serial data to be loaded into the TSA7887 s control register is applied at the din pin. serial data is loaded into the adc from the host processor on low - to - high sclk transitions (see the control register section for additional information ). configuring the TSA7887 a s a single - channel, read - only adc can be achieved by hard - wiring the din pin to gnd or by applying a logic lo w at all times at the din pin . 7 dout serial data out put: the TSA7887s conversion result is available on this pin . serial data is transferred out of the ts7887 on high - to low transitions of sclk. the 12 - bit conversion result is comprised of four leading zeros followed by the 12 bits of con version data formatted msb first. thus, a total of 16 sclk high - to - low transitions transfers the conversion res ult to the host processo r as shown in the corresponding timing diagram of figure 14 . 8 sclk serial - clock input: sclk is used for (3) purposes: a) to load serial data from the host processor into the TSA7887s control register on low - to - high sclk transitio ns; b) to transfer the 12 - bit conversion result to the host processor on high - to - low sclk transitions; and c) to control the TSA7887s conversion process.
ts a7887 page 8 TSA7887ds r1p0 rt f ds TSA7887 control register description the TSA7887s write - only control register is 8 - bit s wide . serial adc configuration d ata is up loaded from the host processor at the TSA7887s din pin on low - to - high sclk transitions . s erial input data is uploaded to the TSA7887 simultaneously as the conversion result is transferred out of the TSA7887. all serial data transfers require 16 serial clocks transitions . a fter a high - to - low cs transition signal , s erial data available on the first eight low - to - high sclk transitio ns is transferred in to the control register. t he first bit in the serial data stream is always interpreted as the msb . upon initial power - up, the TSA7887s default control register bit is cleared to all zeros ( all 0 s ). table 1 lists the functions of the control registers 8 bits. table 1 . TSA7887s 8 - bit control register content description d b7 (msb) d b6 d b5 d b4 d b3 d b2 d b1 d b0 (lsb) dontc zero ref sin/dual ch zero pm1 pm0 d b x label comment 7 dontc control register db7: bit status of db7 is dont care . in other words, the db7 bit can be a 0 or a 1 . 6 zero control register db6: to ensure correct ts7887 operation, control register db6 status must always be a zero (0) . 5 ref control register db5 C internal voltage reference configuration : the status of db5 determines whether the TSA7887s internal voltage reference is enabled or disabled. a 0 in the db5 location will enable the TSA7887s internal voltage reference (default condition). to di sable the TSA7887s internal voltage reference, a 1 must be written into db5s register location. 4 sin/dual control register db4 - single - channel/dual - channel configuration . control register db4 configures the TSA7887 as a single - channel or two - channel adc. loading a zero (0) into this register location configures the TSA7887 for single - channel operation with the ain1/v ref pin configured to for internal vref operation (default configuration) . in this case, the analog input signal range is 0v to vref. loading a one (1) in to this register location configures the TSA7887 for two - channel operation with the ain1/vref pin configured to its ain1 function as the second analog input. in addition, t h e conversion processs reference voltage is internally connected to vdd. in this case, the analog input signal range is 0v to vdd. to obtain best performance from the TSA7887 in two - channel operation , the adcs intern al reference should be disabled; that i s, a 1 should be loaded into db5s register location. 3 ch control register db3 - c hannel select bit : the bit status of db3 determines on which channel the TSA7887 is converting. when the adc is configured for dual - channel operation, db3 determines which channel is converted on the next conversion cycle . when db3 is a zero ( a 0) , the ain0 input is selected and, when db3 is a one ( a 1) , the ain1 input is selected . db3 should be a zero (0) when the TSA7887 is configured for s ingle - channel operation. 2 zero control register db 2 : to ensure correct ts7887 operation, control register db 2 status must always be a zero (0). 1 pm1 control register db1 and db0 - power management operating modes: db1 and db0 are decoded to configure the TSA7887 into one of four operating modes as shown in table 2 . 0 pm0 table 2 . TSA7887s power management op erating modes pm1 pm0 mode 0 0 pm mode 1: in this operating mode, the TSA7887s power - down mode is enabled if its cs input is a one ( a 1) and is operating in full - power mode when its cs input is a zero ( a 0). thus, the TSA7887 is powered down on a low - to - high cs transition and is powered up on a high - to - low cs transition. 0 1 pm mode 2: in this operating mode and regardless of the status of any of the logic inputs , the TSA7887 is always fully powered up . 1 0 pm mode 3: in this operating mode, the TSA7887 is automatically powered down at the end of each conversion regardless of the state of the cs input. adc w ake - u p time from full shutdown is 5s and system design should ensure that at least 5s have elapsed before attempting to perform a conversion in this mode; otherwise, an invalid conversion result may occur. 1 1 pm mode 4: in this operating mode, the TSA7887 is configured for standby operation after conversion. s ections o f the TSA7887 are powered down; however, the internal 2.5 - v reference voltage remains powered up. while pm mode 4 is similar to pm mode 3, pm mode 4 operation allows the TSA7887 to power up much f aster. for optimal performance, t he control registers ref bit (db5) should be a zero (0) to ensure the internal reference is enabled /remains enabled .
TSA7887 TSA7887ds r1p0 page 9 rtfds description of operation the TSA7887 is a single - supply, low - power , single /dual - channel , 12 - bit successive - approximation adc with an easy - to - use serial interface . the adc can be operated from a 3 v supply ( 2.7v to 3.6v) or from a 5 v supply ( 4.75v to 5.25v ) . when operated from either a 3 v or 5 v supply, the TSA7887 can operate at throughput rates up to 125 k sps wh en a n external 2 mhz clock is applied . in 8 - pin soic and msop packages, t he TSA7887 integrates a 2.5 - v reference, a high - speed track/hold, a successive - approximation adc , and a serial digital interface. an external serial clock is used to transfer data to/ from the adc and controls the TSA7887s conversion process. the TSA7887 can be configured for single - or two - channel operation . when configured as a single - channel adc , the analog input range is 0 to v ref (where an externally applied v ref , if used, can range between 1.2 v and v dd ). when the TSA7887 is configured for two - channel applications , the analog input range on each channel is set internally from 0 v to v dd . if the TSA7887 is configured for single - channel operation, the TSA7887 can be operated in a read - only mode by applying a logic low at all times to the din pin (pin 6) or by hard - wiring the din pin permanently to gnd. for maximum flexibility to address multiple co nfigurations based on the application , the din input can be used to load adc configuration data from a host processor into the TSA7887s 8 - bit c ontrol r egister. TSA7887 operation and transfer function the TSA7887 is a successive - approximation adc, the core of which is a charge - redistribution dac. figure 1 illustrates an equivalent circuit for the TSA7887 in signal acquisition phase . here, s witch sw1 is in position a and switch sw2 is closed. with the sampling capacitors terminals connected to the analog input on one side and ref on the other, the analog signal is acquired. during the acquisition phase, the inputs to the comparator are balanced since both inputs are connected to ref. during the conversion phase as shown in the equivalent circuit in figure 2 , switch sw1 is moved from position a to gnd at position b and switch sw2 is opened. at this point in time, the inputs to the comparator become unbalanced. the TSA7887s control logic and the charge - redistribution dac work together to add or subtract fixed packets of charge from the sampling capacitor to balance once again the comparator input terminals . a t the time when the comparator is rebalanced, the conversion process is complete and the adcs control logic generates the adc serial output conversion data. figure 3 illustrates t he ideal transfer function for the TSA7887 where t he output data is cod ed straight binary. thus, t he designed code transitions occur at successive integer lsb values (that is, at 1 lsb, at 2 lsb s , etc ) where t he lsb size is v ref /4096. figure 1: TSA7887s acquisition phase equivalent circuit figure 2 : TSA7887 s conversion phase equivalent circuit figure 3: TSA7887s unipolar transfer function for straight binary digital data.
ts a7887 page 10 TSA7887ds r1p0 rt f ds t ypical application circuit figure 4 shows a typical application circuit for the TSA7887 where t he adcs gnd pin is connected to the analog ground plane of the system. in this application circuit, t he TSA7887 has been configured for two - channel operation so the adcs v ref is internally connected to v dd ; as a result, the analog input range on either analog input is 0 v to v dd . it is always considered good engineering practice to b ypass the adcs vdd with good quality capacitors with short leads (surface - mount components are preferred) and located a very short distance from the adc. the conversion result at the dout pin is a 16 - bit word with four leading zeros followed by the msb of the 12 - bit conversion result. in low - power applications , automatic - power - down - at - the - end - of - conversion mode s (pm modes 3 or 4) should be used to improve the adcs power consumption - versus - throughput rate performance. for additional information on the TSA7887s four power management operating modes, please consult the operating modes section of the datasheet . a nalog input details an equivalent circuit of t he analog input structure of the TSA7887 is illustrated in figure 5 where d iodes d1 and d2 serve as esd - clamp protection for the analog inputs. since there are diodes from the analog input to both vdd and gnd, it is important any forward conduction of current in d1 or d2 is avoided. thus, the analog input signal should never exceed th e either vd d or gnd by more than 200 mv. even though t he maximum current these diodes can conduct without causing irreversible damage to the adc is 20 ma , any small amount of forward diode current into the substrate because of an overvoltage condition on an unselected channel can cause inaccurate conversion results on the selected channel. attributed to parasitic package pin capacitance, c apacitor c1 in figure 5 is typically about 1 pf. resistor r1 is the equivalent series resistance of the TSA7887s input multiplexer and input sampling switch and is approximately 100 . capacitor c2 is the adc sampling capacitor and has a typical capacitance of 10 pf . in signal - acquisition ( or ac) applications, the use of an external r - c low - pass filter on either or both analog inputs can be useful in removing out - of - band high - frequency components from the analog input signal . in applications where harmonic distortion and signal - to - noise ratio performance are important , the analog input (s) should be driven from a low - impedance source. l arge source impedances will affect significantly the TSA7887s ac performance. to lower the driving - point impedance level may impose the use of an input buffer amplifier. the optimal choice for the external drive op amp will be determined by application re quirements as well as the TSA7887s dynamic performance . when the analog input is not driven by an external amplifier , the driving - point source impedance should be low. the maximum source impedance will depend upon the amount of total harmonic distortion (thd) that can be tolerated in the application. thd will i ncrease as the source impedance increases figure 4: TSA7887's typical application circuit . figure 5: TSA7887s analog input equivalent circuit. input frequency - khz total harmonic distortion - dbc v dd = 5v 5v external reference - 65 - 75 - 85 - 90 0.2 1 0 3 0 50 2 0 - 60 figure 6 : TSA7887 thd vs analog input frequency rin = 50 ? , c in = 2.2nf rin = 10 ? , c in = 10nf - 70 - 80 40
TSA7887 TSA7887ds r1p0 page 11 rtfds and performance will degrade. figure 6 illustrates how the TSA7887s harmonic performance as a function of frequency is affected by different source impedances . the TSA7887s internal 2.5 - v reference using the ref bit (the db5 bit) in the TSA7887s control register, t h e TSA7887s internal 2.5 - v reference can be enabled ( db5 clear ed to 0) or disabled ( db5 set to 1 ) . if enabled (the default condition), the internal voltage reference can be used in applications for other purposes and, if this is desired, the reference should be buffered by an external, precision op amp. if an external, precision voltage reference is to be used instead of the TSA7887s internal reference, the internal reference is automatically overdriven. in this case , the TSA7887s internal reference should be disabled by setting the ref bit in the control register . when the internal reference is disabl ed, switch sw1 as shown in figure 7 opens and the input impedance seen at the ain1/v ref pin is the reference buffer s input impedance , approximately in the gigaohm range (g?) . when the internal reference is enabled, the input impedance at the ain1/vref pin is typically 10k. when the TSA7887 is configured for two - channel operation , the TSA7887 s reference is set internally to v dd . TSA7887s p ower - down o perating modes the TSA7887 provides flexible power management to allow the user to achieve the best power performan ce for a given throughput rate. the four power management options are selected by programming the TSA7887s power management bits ( pm bits pm1 and pm0) in the control register as summarized in table 6. when the pm bits are programmed for either of the auto power - down modes (pm mode 3 or 4) , the TSA7887 is power ed - down on the 16th low - to - high sclk transition after a high - to - low cs transition. the first high - to - low sclk transition after a high - to - low cs transition powers - up the TSA7887 again. when the TSA7887 is programmed in pm mode 1 (i.e. , [ pm1 , pm0 ] = [ 0 ,0] , the default condition ), the TSA7887 is powered down on a low - to - high cs transition and power s up from shutdown on a high - to - low cs transition . i f the cs pin is toggled low - to - high during the conversion in this operating mode, the adc is immediately powered down . cold - start and standby power - up delay times when v dd is first applied to the TSA7887 (in other words, from cold start - up) , the adc powers up in pm mode 1 ([ pm1 , pm0 ] = [ 0 ,0]). upon a subsequent high - to - low cs transition, the TSA7887s power - up delay time is approximately 5s when using an external voltage reference in single - channel operation or when the TSA7887 is powered up from standby mode (pm mode 4) , its power - up delay time is approximate ly 1s because the internal reference has been either disabled (refer to control register db5) or the internal reference has remained powered up (via pm mode 4) . since the TSA7887s power - up delay time pm mode 4 is very short , power ing up the adc and execut ing a conversion with valid results in the same read/write operation is feasible. TSA7887 p ower c onsumption vs . t hroughput rate c onsiderations in operating the TSA7887 in auto - shutdown mode (pm mode 3) , in auto - standby mode (pm mode 4) , or in pm mode 1, the average power drawn by the TSA7887 decreases at lower throughput rates. as shown in figure 8 , the average power drawn from figure 7 : TSA7887s integrated 2.5 - v vref circuitry. throughput rate - ksps power consumption - m w 1 0.1 0.01 0 10 30 50 20 10 figure 8 : TSA7887 power consumption vs throughput rate v dd = 3v sclk = 2mhz v dd = 5v sclk = 2mhz 40
ts a7887 page 12 TSA7887ds r1p0 rt f ds the supplies by the adc is commensurately reduced the longer the TSA7887 remains in a power ed - down state . for example, consider the following TSA7887 application configuration: (a) the adc is powered from vdd = 5v and is configured for pm mode 3 (that is, [pm1, pm0] = [1 ,0], where the adcs internal reference is enabled and the adc automatically powers down after the conversion is completed); and (b) the adc operates at a throughput rate of 10 k sps with a 2 - mhz sclk . given the above configuration, the TSA7887s power consumption during normal operation is 3.5mw at v dd = 5 v (0.7ma x 5v). since its power - up delay time is 5 s and its conversion - plus - acquisition time is ~7.75 s (t convert + t acq = 14.5 x t sclk + 1.5 x t sclk = 15.5 x t sclk ), the TSA7887 consumes 3.5 mw for 12.75 s during each conversion cycle. since the conversion cycle time (100 s ) is the reciprocal of the adcs throughput rate (10ksps), the average power consumed by the TSA7887 during each conversion cycle is (12.75/100) (3.5mw), or 446.25 w. if the adc s configuration were unchanged and , if the supply voltage were then reduced to 3v, the power consumed by the adc would then be 2.1mw (0.7ma x 3v). since the total time required for power - up, acquisition, and conversion remains at 12.75 s , the average power consumed during e ach cycle at a 10 - ksps throughput rate is (12.75/100) (2.1mw), or 267.75 w. t he TSA7887s power consumption vs. throughput rate when configured for automatic shutdown post conversion and operating on both 5v and 3v supplies is illustrated in figure 8 . power management operating modes d esigned to provide flexible power consumption profiles, the TSA7887 incorporates four different operating modes to optimize the adcs power c onsumption /throughput - rate ratio . as previously described in table 6, t he four different modes of operation in the TSA7887 are controlled by the pm1 and pm0 bits of the c ontrol r egister. also mentioned previously, the TSA7887 can be configured as a read - only adc by forcing an all zeros ( 0 s ) condition in the control register . this can be easily done by applying a logic low at all times to the din pin or hard - wiring the din pin directly to gnd . power management mode 1 operation: [ pm1 ,pm0] = [ 0 , 0 ] power management operating mode 1 is used to control the TSA7887s power - down using the cs pin. whenever the cs pin is low, the TSA7887 is fully powered up; whenever the cs pin is high, the TSA7887 is completely powered down . when the cs pin is toggled h igh - to - low, all internal circuitry starts to power up where it can take as long as 5s for the TSA7887 s internal circuitry to power up comple tely. as a result, any conversion start sequence should not be initiated during this initial 5s power - up delay . figure 9 shows a general oper a ting diagram of the TSA7887 in pm mode 1 . the analog input signal is sampled on the second low - to - high sclk transition following the initial high - to - low cs transition . system timing design should incorporate a 5 - s delay between the high - to - low cs transition and the second low - to - high sclk transition . in microcontroller applications, this is achiev ed by figure 9: TSA7887s power management mode 1 operation diagram.
TSA7887 TSA7887ds r1p0 page 13 rtfds driving the cs pin from one of the host processors port lines and ensuring that the serial data read (from the microcontroller s seri al port) is not initiated for at least 5 s. in dsp applications, where the cs signal is derived typically from the dsps serial frame synchronization port , it is usually not possible to separate a high - to - low cs transition and a second low - to - high sclk transition by up to 5s without affecting the dsp system serial clock speed. therefore, system timing design should incorporate a write to the TSA7887s cont rol register to terminate pm mode 1 operation and program the adc into pm mode 2 ; that is , by writing [ pm1 , pm0 ] = [0, 1 ] into the TSA7887s control register . t o get a valid conversion result , a second conversion must be initiated when the adc is powered up. a write operation that takes place w ith this second conversion can program the adc back into pm mode 1 where the power - down operation is enabled when the cs pin is toggled high power management mode 2 operation : [pm1,pm0] = [0,1] r egardless of the status of the cs signal, the TSA7887 remains fully powered up i n this mode of operation. pm mode 2 should be used for fastest throughput rate performance because the system timing design does not need to incorporate the TSA7887s 5 - s power - up delay time . figure 10 shows the general operating diagram for the TSA7887 in pm mode 2 . serial d ata programmed into the TSA7887 at the din input during the first eight clock cycles of data transfer are loaded to the control register. for the TSA7887 to remain in pm mode 2, system timing design must always write [pm1, pm0] = [0,1] into the control register on every serial input data transfer. a high - to - low cs transition initiates the conversion sequence and the analog input signal is sampled on the second low - to - high sclk transition . sixteen serial clock cycles are required to complete the conversion and to transfer the conversion r esult to the host processor . a nother conversion can be initiated immediately by toggling the cs pin low again o nce data transfer is complete (that is, once the cs signal is toggled high). power management mode 3 operation: [pm1, pm0] = [1,0] in this mode, the TSA7887 is automatically powered down at the end of every conversion. it is similar to pm mode 1 except that the status of the cs signal in pm mode 3 does not have any effect on the power - down status of the TSA7887 . figure 11 shows the g eneral operating diagram of the TSA7887 in pm mode 3 . on the first high - to - low sclk transition after cs is toggled low, all TSA7887s internal circuitry starts to pow er up. similarly to pm mode 1, it can take as long as 5s for the TSA7887 s internal circuitry to power up comple tely . as a result, any conversion start sequence should not be initiated during this initial 5 - s power - up delay . the analog input signal is sampled on the second low - to - high sclk transition following the high - to - low cs transit ion. as shown in figure 18, s ystem timing design should incorporate a 5 - s delay between the first high - to - low scl transition and the second low - to - high sclk transition after the high - to - low cs transition . figure 10: TSA7887s power management mode 2 operation diagram.
ts a7887 page 14 TSA7887ds r1p0 rt f ds in microcontroller applications (or in systems with a slow serial clock) , the system timing design can be devised to accommodate this timing alignment by assigning the cs signal to one of the port lines and then adjusting the timing such that the serial data read (from the microcontroller s seri al port) is not initiated for at least 5s . however, in systems with higher speed serial clocks (not unlike high - speed serial - clock dsp applications) , it may not be possible to insert a 5s delay between adc power up and the first lo w - to - high sclk transition . therefore, system timing design should incorporate a write to the TSA7887s control register to terminate the adcs p m mode 3 operation and program the TSA7887 into pm mode 2; that is , by writing [pm1,pm0] = [0,1] into the tsa788 7s control register. t o get a valid conversion result , a second conversion must be initiated when the adc is powered up C see figure 19 . a write operation that takes place w ith this second conversion can program the adc back into pm mode 3 where the power - down operation is enabled when the conversion sequence terminates . power management mode 4 operation: [pm1,pm0] = [1,1] in pm mode 4 , the TSA7887 is automatically placed in standby (or sleep) mode at the end of every conversion. in this mode, all i nternal circuitry is powered down except for the internal 2.5 - v reference. pm mode 4 is similar to pm mode 3 ; in this case, the power - up delay time is much shorter ( 1s vs 5s ) because the internal reference remains powered up at all times. figure 13 shows the general operating diagram of the TSA7887 in pm mode 4 . on the first high - to - low sclk transition after the cs pin is toggled low , the TSA7887 is powered up out of its standby mode . since the TSA7887s power - up delay time pm mode 4 is very short, powering up the adc and executing a conversion with valid results i n the same read/write operation is feasible. the analog input signal is sampled on the second low - to - high sclk transition figure 11: TSA7887s power management mode 3 operation diagram for slow - sclk microcontrollers. figure 12: TSA7887s power management mode 3 operation diagram for fast - sclk microcontrollers and dsps.
TSA7887 TSA7887ds r1p0 page 15 rtfds following the high - to - low cs transition . at the end of conversion ( after the last low - to - high sclk transition ), the adc is powered down automatically back into its standby mode. the TSA7887s s erial i nterface description figure 14 sh ows the detailed timing diagram for TSA7887s serial interfac e . the serial clock provides the conversion clock and also c ontrols the transfer of data to/ from the TSA7887 during conversion. the cs signal initiates the serial data transfer and controls the TSA7887s conversion process. in pm modes 1, 3, and 4, a high - to - low cs transition powers up the adc. in all cases, the cs signal gates sclk to the TSA7887 and sets the adcs internal track - and - hold into track mode. the analog input signal is then sampled on the second low - to - high sclk transition following the high - to - low cs transition . thus, the analog input signal is acquired during the first 1.5 sclk clock cycles (t acq ) after the high - to - low c s transition . in modes where the high - to - low cs transition powers up the adc, the acquisition time must include a 5 - s power - up delay . the adcs internal track - and - hold moves from track mode to hold mode on the second low - to - high sclk transition and a conversion is also initiated on this transition . the conversion process takes an additional 14.5 sclk cycles to complete. after the conversion is completed, a subsequent low - to - high cs transition sets the serial data bus back into a high - z (or three - state ) condition. a new conversion can be initiated i f the cs signal is left low . in dual - channel operation, the current conversion result is associated to the selected analog channel programmed during the previous write cycle to the control register. th erefore, in dual - channel operation, the system code design must perform a channel address write for the next conversion while the current conversion is in progress. writing serial data to the control register always takes place and occurs on the first eig ht low - to - high sclk transitions. however, the TSA7887 can be configured as a read - only device by physically figure 14: TSA7887s detailed serial interface timing diagram. figure 13: TSA7887s power management mode 4 operation diagram.
ts a7887 page 16 TSA7887ds r1p0 rt f ds loading all zeros (0s) into the control register every time, by applying a logic low to the din pin at all times, or by hard - wiring the din pin to gnd. when the TSA7887 is configured in write/read modes, system code design must be designed always to load the correct data onto the din line when reading data from the TSA7887. sixteen serial clock cycles are required to perform the conversion proces s and to transfer data to/access data from the TSA7887. in applications where the first serial clock transition following a high - to - low cs transition is a high - to - low sclk transition , dout transitions from a high - z state to a first leading zero; thus, the first low - to - high sclk transition generates the first leading zero on dout. in applications where the first serial clock transition following a high - to - low cs transition is a low - to - high sclk transition, the first leading zero may not be set up in time for the host processor to read it correctly. however, subsequent dout bits are transferred out on high - to - low sclk transitions so that they are ready for the host processor on the following low - to - high sclk transition. thus, the second leading zero is transfe rred out on the high - to - low sclk transition subsequent to the first low - to - high sclk transition. therefore, douts final bit in the data transfer is valid on the 16th low - to - high sclk transition, having been transferred out of the adc on the previous high - to - low sclk transition. interfacing the TSA7887 to industry - standard microprocessors and dsps the serial interface on the TSA7887 allows the adc to be directly connected to a number of many microprocessors and dsps . h ow to interface the TSA7887 with some of the more common microcontroller and dsp serial interface protocols is covered in this section . a TSA7887 to tms320c5x dsp interface with peripheral serial devices like the TSA7887, the tms320c5xs serial interface has a continuous serial clock and frame synchronization signals to time the data transfer operations. a single logic inverter is the only glue logic required between the tms3 20c5xs clx output and the TSA7887 scl input and is illustrated in the connection diagram of figure 15 . the tms320c5xs serial port is configured to operate in burst mode using the tms320c5xs internal clx (serial clock transmit) and fsx (frame sync tra nsmit) programmed as the TSA7887s cs input . the tms320c5xs serial port control register (spc) must be configured in the following manner: table 3: tms320c5x serial port control register setup fo fsm mcm txm 0 1 1 1 a TSA7887 to adsp - 21xx dsp interface the TSA7887 is easily interfaced to the adsp - 21xx (or equivalent) family of dsps using an inverter between the adsp - 21xx s serial clock and the TSA7887 as shown in figure 16 . the adsp - 21xx s sport control register should be configured in alternate framing mode as shown in table 4 and t he adsp - 21xxs serial clock frequency is set in its sclkdiv register. table 4: sport0 control register setup bit(s) setting description tfsw, rfsw 1 alternative framing invrfs, invtfs 1 active - low frame signal dtype 00 right justified data slen 1111 16 - bit data word isclk 1111 internal serial clock tfsr, rfsr 1 frame every word irfs 0 itfs 1 figure 15: interfacing the TSA7887 to tsm320c5x - type dsps. figure 16 : interfacing the TSA7887 to adsp - 21xx - type dsps.
TSA7887 TSA7887ds r1p0 page 17 rtfds with the adsp - 21xxs tfs and rfs pins of its sport connected together, the tfs is configured as an output and rfs configured as an input. the frame synchronization signal generated on the tfs output serves as the TSA7887s cs input. in this example, howeve r, since a timer interrupt is used to control the sampling rate of the adc, it may not be possible to perform equidistant sampling (a required criterion in all signal processing applications) under certain application conditions. the adsp - 21xxs timer reg isters are configured in such a manner that an interrupt is generated internally at the required sample interval. when the timer interrupt is received, an adc control word is transmitted at the dt output with tfs. the tfs signal is then used to control the rfs and hence the data read from the TSA7887. when the instruction to transmit with tfs is executed (that is, ax0 = tx0), the state of the sclk is checked. the dsp waits until the sclk has toggled high - to - low - to - high before a transmission will commence. i f the timer and sclk values are set such that the instruction to transmit occurs on or near the low - to - high sclk transition, data may be transmitted or the dsp may wait to transmit data until the next clock edge. for example, consider an adsp - 2111 that ha s been chosen as the host processor. since it has a 16 - mhz master clock frequency, a sclkdiv value of 3 is necessary to program its sport serial clock output to operate at 2mhz for the TSA7887 (16mhz 2 3 = 2mhz); thus, eight master clock periods will el apse for every one TSA7887 sclk period. if the adsp - 2111s timer registers are loaded with a value of 803, 100.5 sclks will occur between interrupts and subsequently between transmit instructions. because the transmit instruction occurs on an sclk edge, no n - equidistant sampling is the result. the dsp will implement equidistant sampling only if the number of sclks between interrupts is a whole integer number. a TSA7887 to dsp56xxx dsp interface connecting the TSA7887 for use with freescales (nee motorola s) dsp56xxx family of dsps is shown in figure 17 where an inverter is used between the dsp56xxxs sc output and the TSA7887s scl input. the dsp56xxxs ssi (synchronous serial interface) is configured in synchronous mode (syn bit = 1 in crb) with an inte rnally generated 1 - bit clock period frame sync for both tx and rx (bits fsl1 = 1 and fsl0 = 0 in crb). word length is set to 16 by setting bits wl1 = 1 and wl0 = 0 in cra. a TSA7887 to 68hc11 microcontroller interface connecting the TSA7887 to freescales 68hc11 (nee motorolas mc68hc11) is shown in figure 18 . the microcontrollers serial peripheral interface (spi) i s configured for master mode (mstr = 1) with its clock polarity bit (cpol) set to 1 and clock phase bit (cpha) set to 1. serial data transfer from the TSA7887 to the 68hc11 requires two 8 - bit transfers and the 68hc11s spi is configured by writing to the s pi control register (spcr) consult the 68hc11 user manual for more information. a TSA7887 to 8051 microcontroller interface using the parallel port of legacy 8051 - type (or equivalent) microcontrollers, a serial interface to the TSA7887 can be designed as shown in figure 19 . as a result, full duplex serial transfer to be implemented. the technique involves bit - banging one of t he the microcontrollers i/o ports (for example, p1.0) to generate a serial clock and using figure 18 : interfacing the TSA7887 to 68hc11 - type microcontrollers. figure 17 : interfacing the TSA7887 to dsp56xx x - type dsps. figure 19 : interfacing the TSA7887 to legacy 8051 - type microcontrollers .
ts a7887 page 18 TSA7887ds r1p0 rt f ds two other i/o ports (for example, p1.1 for dout and p1.2 for din ) to transfer data from / to the TSA7887. a TSA7887 to pic16c6x/pic16c7x microcontroller interface as shown in figure 20 , the connection between the TSA7887 and the pic16c6x/pic16c7x is simple and does not require any glue logic circuits. the pic16c6x synchronous serial port (ssp) is configured as an spi master with its clock polarity bit set to 1 by wr iting to the synchronous serial port control register (sspcon). in this example, i/o port ra1 is being used to generate the TSA7887s cs signal. since this microcontroller family only transfers eight bits of d ata during each serial transfer operation, two consecutive read/write operations are required. for additional information, please consult the pic16/pic17 microcontroller user manual . applications informa tion ground plane management and layout for best performance, printed circuit boards should always be used and wire - wrap boards are not recommended. good pc board layout techniques ensure that digital and analog signal lines are kept separate from each other, analog and digital (especially clock) lines are not routed parallel to one another, and high - speed digital lines are not routed underneath the adc package. a contiguous analog ground plane should be routed under the TSA7887 to avoid digital noise coupling. a single - point analog ground (star ground point) should be created at the adcs gnd and separate from any digital logic ground. all analog grounds as well as the adcs gnd pin should be connected to the star ground. no other digital system ground should be made to this ground connection . for lowest - noise operation, the ground return to the star grounds power supply should be low impedance and as short as po ssible. even though the TSA7887s exhibits excellent supply rejection as shown in th typical operating characteristics , it is always considered good engineering practice to prevent h igh - frequency noise on the TSA7887s vdd power supply from affect ing the adcs high - speed comparator. therefore, the vdd supply pin should be bypassed to the star ground with 0.1f and 1 0 f capacitors in parallel and placed close to the adcs pin 2 as was shown in figure 4 . component lead lengths should be very short for optima l supply - noise rejection. if the power supply is very noisy, an optional 10 - resistor inserted in series with the TSA7887s vdd pin can be used in conjunction with the bypass capacitors to form a low - pass filter. evaluating the TSA7887 s dynamic performance the recommended layout for the TSA7887 is outlined in the demo board manual for the TSA7887. the demo board kit inc ludes a fully assembled/ tested demo board and documentation describing how to evaluate the TSA7887s dynamic performance using t ouchstone semiconductors proprietary tsda - vb data acquisition/capture kit. figure 20: interfacing the TSA7887 to pic16c6x/pic16c7x - type microcontrollers.
TSA7887 TSA7887ds r1p0 page 19 rtfds package outline draw ing 8 - pin msop package outline drawing (n.b., drawings are not to scale) 0 . 6 5 r e f 3 . 1 0 m a x 2 . 9 0 m i n 0 . 9 5 m a x 0 . 7 5 m i n 0 . 1 5 m a x 0 . 0 5 m i n s e a t i n g p l a n e 5 . 0 8 m a x 4 . 6 7 m i n 3 . 1 0 m a x 2 . 9 0 m i n 0 ' - - 6 ' d e t i l d e t i l 0 . 2 5 0 . 7 0 m a x 0 . 4 0 m i n 0 . 2 3 m a x 0 . 1 3 m i n n o t e : 1 . p a c k a g e l e n g t h d o e s n o t i n c l u d e m o l d f l a s h , p r o t r u s i o n s o r g a t e b u r r s . 2 . p a c k a g e w i d t h d o e s n o t i n c l u d e i n t e r l e a d f l a s h o r p r o t u s i o n s . 3 . c o n t r o l l i n g d i m e n s i o n i n m i l i m e t e r s . 4 . t h i s p a r t i s c o m p l i a n t w i t h j e d e c m o - 1 8 7 v a r i a t i o n s a a 5 . l e a d s p a n / s t a n d o f f h e i g h t / c o p l a n a r i t y a r e c o n s i d e r e d a s s p e c i a l c h a r a c t e r i s t i c . 1 2 8 0 . 3 8 m a x 0 . 2 8 m i n 0 . 1 0 m a x g a u g e p l a n e 1 . 1 0 m a x 0 . 2 7 r e f 0 . 1 2 7 0 . 2 3 m a x 0 . 1 3 m i n 0 . 3 8 m a x 0 . 2 8 m i n
ts a7887 page 20 touchstone semiconductor, inc. TSA7887ds r1p0 630 alder drive, milpitas, ca 95035 rt f ds +1 (408) 215 - 1220 ? www.touchstonesemi.com package outline draw ing 8 - pin soic package outline drawing (n.b., drawings are not to scale) information furnished by touchstone semiconductor is believed to be accurate and reliable. however, touchstone semiconductor does not assume any responsibility for its use nor for any infringements of patents or other rights of third parties that may result from its use , and all information provided by touchstone semiconductor and its suppliers is provided on an as is basis, without warranty of any kin d . touchstone semiconductor reserves the right to change product specification s and product descriptions at any time without any advance notice. no license is granted by implication or otherwise under any patent or patent rights of touchstone semiconductor. touchstone semiconductor assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using touchstone semiconductor components. to minimize the risk associated with customer products and applicatio ns, customers should provide adequate design and operati ng safeguards. trademarks and registered trademarks are the property of their respective owners. 1 . 2 7 t y p 0 . 3 3 - 0 . 5 1 4 . 8 0 - 5 . 0 0 3 . 7 3 - 3 . 8 9 0 - 8 3 . 8 1 C 3 . 9 9 1 2 2 n o t e s : d o e s n o t i n c l u d e m o l d f l a s h , p r o t r u s i o n s o r g a t e b u r n s . m o l d f l a s h , p r o t r u s i o n s o r g a t e b u r r s s h a l l n o t e x c e e d 0 . 1 5 m m p e r s i d e . d o e s n o t i n c l u d e i n t e r - l e a d f l a s h o r p r o t r u s i o n s . i n t e r - l e a d f l a s h o r p r o t r u s i o n s s h a l l n o t e x c e e d 0 . 2 5 m m p e r s i d e . l e a d s p a n / s t a n d o f f h e i g h t / c o p l a n a r i t y a r e c o n s i d e r e d a s s p e c i a l c h a r a c t e r i s t i c ( s ) . c o n t r o l l i n g d i m e n s i o n s a r e i n m m . t h i s p a r t i s c o m p l i a n t w i t h j e d e c s p e c i f i c a t i o n m s - 0 1 2 l e a d s p a n / s t a n d o f f h e i g h t / c o p l a n a r i t y a r e c o n s i d e r e d a s s p e c i a l c h a r a c t e r i s t i c . 1 2 l e a d f a r m e t h i c k n e s s 0 . 1 9 C 0 . 2 5 5 . 8 0 C 6 . 2 0 0 . 1 0 C 0 . 2 5 1 . 7 5 m a x 0 . 1 0 m a x 7 ' r e f a l l s i d e 7 ' r e f a l l s i d e 0 . 7 6 m a x 0 . 6 6 m i n 0 . 4 0 6 C 0 . 8 6 3 0 . 5 4 6 r e f 0 . 4 8 m a x 0 . 2 8 m i n 4 5 ' a n g l e 0 . 2 5 5 . 6 . 1 . 3 2 C 1 . 5 2 g a u g e p l a n e 3 . 4 .

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